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2017 Hybrid, Adaptive, and Reconfigurable Fault Tolerance (HARFT) C. Wilson, S. Sabogal, A. George, A. Gordon-Ross PDF
2017 OpenCL-based design pattern for line rate packet processing J. Khan, P. Athanas, S. Booth, J. Marchall PDF
2017 Comparative Analysis of Parallel OPIR Compression on Space Processors A. Ho, E. Shea, A. George, A. Gordon-Ross PDF
2017 Vivado Design Interface: An Export/Import Capability for Vivado FPGA Designs T. Townsend, B. Nelson PDF
2017 A Test Bed Study of Network Determinism for Heterogeneous Traffic Using Time-Triggered Etherne A. Starke, M. Ford, D. Kumar, J. McNair, A. Bell PDF
2017 Overlay-based side-channel countermeasures: A case study on correlated noise generation A. Baylis, G. Stitt, and A. Gordon-Ross PDF
2017 A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance D. Wilson, A. Shastri, and G. Stitt.
2017 Exploration of TMR Fault Masking with Persistent Threads on Tegra GPU SoCs A. Milluzzi, A. George, PDF
2017 A scalable, low-overhead finite-state machine overlay for rapid FPGA application development D. Wilson and G. Stitt, PDF
2017 Optimizing FPGA Performance, Power, and Dependability with Linear Programming N. Wulf, A. George, A. Gordon-Ross PDF
2017 AutoMatch: An Automated Framework for Relative Performance Estimation and Workload Distribution on Heterogeneous HPC Systems A. Helal, W. Feng, C. Jung, Y. Hanafy PDF
2017 Comparative Analysis of Present and Future Space-Grade Processors with Device Metrics T. Lovelly, A. George PDF
2017 Software and Firmware Co-development using High-Level Synthesis N. Ghanathe, A. Madorsky, H. Lam, D. Acosta, A. George, M. Carver, Y. Xia, Jyothishwara, A., Hansen, M. PDF
2017 Robotomata: A Framework for Approximate Pattern Matching of Big Data on an Automata Processor X. Yu, K. Hou, H. Wang, W. Feng PDF
2017 Using On-Chip Error Detection to Estimate FPGA Design Sensitivity A. Keller PDF
2016 Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs A. Morales-Villanueva, R. Kumar, and A. Gordon-Ross PDF
2016 HISC/R: An Efficient Hypersparse Storage Format for Scalable Graph Processing R. Kirchgessner, G. De La Torre, A. George, V. Gleyzer PDF
2016 An OpenCL Framework for Distributed Apps on a Multidimensional Network of FPGAs Lawande, A. George, H. Lam PDF
2016 Edit Real-Time, Low-Latency Image Processing with High Throughput on a Multi-Core SoC Ramesh, A. George, H. Lam
2016 Computational and Memory Analysis of Tegra SoCs Milluzzi, A. George, H. Lam PDF
2016 A q-gram Birthmarking Approach to Predicting Reusable Hardware K. Zeng, P. Athanas PDF
2016 Novo-G#: A Community Resource for Exploring Large-Scale Reconfigurable Computing with Direct and Programmable Interconnects George, M. Herbordt, H. Lam, A. Lawande, J. Sheng PDF
2016 FPGA-Pipelined Discrete-Event Simulations for Accelerated Behavioral Emulation of Extreme-Scale Systems Pascoe, N. Kumar, K. Alli, H. Lam, G. Stitt, A. George PDF
2016 μCSP: A Diminutive, Hybrid, Space Processor for Smart Modules and CubeSats Wilson, J. MacKinnon, P. Gauvin, S. Sabogal, A. George PDF
2016 Behavioral Emulation for Scalable Design-Space Exploration of Algorithms and Architectures N. Kumar, C. Pascoe, C. Hajas, H. Lam, G. Stitt, A. George PDF
2016 Novo-G#: a Multidimensional Torus-based Reconfigurable Cluster for Molecular Dynamics, A. Lawande, A. George, H. Lam PDF
2016 A Methodology for Estimating Reliability of SmallSat Computers in Radiation Environments Wilson, A. George, B. Klamm PDF
2016 DrSEUs: A Dynamic Robust Single-Event Upset Simulator Carlisle, N. Wulf, J. MacKinnon, A. George PDF
2016 Packing a Modern Xilinx FPGA Using RapidSmith T. Haroldsen, B. Nelson, B. Hutchings PDF
2016 Improving Compression Ratios for High Bit-Depth Grayscale Video Formats Ho, A. George, A. Gordon Ross PDF
2016 A Research Platform for Custom Memory Cube G. Wang, H. Lam, Y. Zou, R. Xavier, S. Gundecha, A. George PDF
2016 Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics J. Richardson, K. Cheng, A. George, H. Lam PDF
2016 A Framework for Evaluating and Optimizing FPGA-based SoCs for Aerospace Computing N. Wulf, A. George, A. Gordon-Ross PDF
2016 Benefits of Complementary SEU Mitigation for the LEON3 Soft Processor on SRAM-Based FPGAs A. Keller, M. Wirthlin PDF
2016 SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing M. Wirthlin, A. Keller, C. McCloskey, P. Ridd, D. Lee, J. Draper PDF
2015 On the Performance, Energy, and Power of Data-Access Methods in Heterogeneous Computing Systems R. Kalidas, M. Daga, K. Krommydas, W. Feng PDF
2015 Partial Region and Bitstream Cost Models for Hardware Multitasking on Partially Reconfigurable FPGAs A. Morales-Villanueva, A. Gordon-Ross PDF
2015 An Automated High-level Design Framework for Partially Reconfigurable FPGAs R. Kumar and A. Gordon-Ross PDF
2015 MACS: A Highly Customizable Low-latency Communication Architecture R. Kumar and A. Gordon-Ross PDF
2015 Comparative Analysis of OpenCL vs. HDL with Image-Processing Kernels on Stratix-V FPGA K. Hill, S. Craciun, A. George, H. Lam
2015 CSP Hybrid Space Computing for STP-H5/ISEM on ISS C. Wilson, A. George, et al. PDF
2015 Memory-Aware Optimization of FPGA-based Space Systems N. Wulf, A. George, A. Gordon-Ross PDF
2015 Performance and Productivity Evaluation of Hybrid-Threading HLS versus HDLs G. Wang, H. Lam, A. George, G. Edwards PDF
2015 In-System Testing of Xilinx 7-Series FPGAs: Part 1-Logic H. Modi, P. Athanas PDF
2015 Low-level PGAS computing on many-core processors with TSHMEM B. Lam, A. George, H. Lam, V. Aggarwal PDF
2015 Discovering Reusable Hardware Using Birthmarking Techniques K. Zang, P. Athanas PDF
2015 A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications A. Shastri, G. Stitt, and E. Riccio PDF
2015 Low-Overhead FPGA Middleware for Application Portability and Productivity R. Kirchgessner, A. George, G. Stitt PDF
2015 CMT-bone: A Mini-App for Compressible Multiphase Turbulence Simulation Software Kumar, Nalini, Mrugesh Sringarpure, Tania Banerjee, Jason Hackl, S. Balachandar, Herman Lam, Alan George, and Sanjay Ranka PDF
2015 Core-level modeling and frequency prediction for DSP applications on FPGAs G. Wang, G. Stitt, H. Lam, A. George PDF