| 2011 |
Platform-Aware Bottleneck Detection for Reconfigurable Computing Applications |
S. Koehler, G. Stitt, and A. George |
PDF |
| 2011 |
An Analytical Model for Multi-Level Performance Prediction of Multi-FPGA Systems |
B. Holland, A. George, H. Lam, and M. Smith |
PDF |
| 2011 |
SHMEM+: A Multilevel-PGAS Programming Model for Reconfigurable Supercomputing |
V. Aggarwal, A. George, C. Yoon, K. Yalamanchili, and H. Lam |
PDF |
| 2011 |
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing |
G. Stitt, A. George, H. Lam, M. Smith, V. Aggarwal, G. Wang, C. Reardon, B. Holland, S. Koehler, and J. Coole |
PDF |
| 2011 |
On the Efficacy of a Fused CPU+GPU Processor for Parallel Computing |
M. Daga, A. Aji, and W. Feng |
PDF |
| 2011 |
Spectral Method Characterization on FPGA and GPU Accelerators |
K. Pereira, P. Athanas, H. Lin, W. Feng |
PDF |
| 2011 |
Address translation optimization for Unified Parallel C multi-dimensional arrays |
O. Serres, A. Anbar, S. G. Merchant, A. Kayi and T. El-Ghazawi |
PDF |
| 2011 |
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping |
C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings |
PDF |
| 2011 |
SCIPS: An Emulation Methodology for Fault Injection in Processor Caches |
N. Wulf, G. Cieslewski, A. Gordon-Ross, and A. George |
PDF |
| 2011 |
Experiences with UPC on TILE-64 processor |
O. Serres, A. Anbar, S. Merchant and T. El-Ghazawi |
PDF |
| 2011 |
Software Fault-Tolerant Techniques for Softcore Processors in Commercial SRAM-Based FPGAs |
N. Rollins and M. Wirthlin |
PDF |
| 2011 |
A Framework for Evaluating High-Level Design Methodologies for High-Performance Reconfigurable Computers |
E. El-Araby, S. Merchant, and T. El-Ghazawi |
PDF |
| 2011 |
High-level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis |
J. Curreri, G. Stitt, and A. George |
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| 2011 |
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation |
Greg Stitt, James Coole |
PDF |
| 2011 |
Reduced-Precision Redundancy on FPGAs |
B. Pratt, M. Fuller, and M. Wirthlin |
PDF |
| 2011 |
Communication Visualization for Bottleneck Detection of High-Level Synthesis Applications |
J. Curreri, G. Stitt, and A. George |
PDF |
| 2011 |
Hardware Module Reuse and Runtime Assembly for Dynamic Management of Reconfigurable Resources |
A. Jara-Berrocal and A. Gordon-Ross |
PDF |
| 2011 |
Partially Reconfigurable System-on-Chips for Adaptive Fault Tolerance |
S. Yousuf and A. Gordon-Ross |
PDF |
| 2011 |
A Static Task Scheduling Framework for Independent Tasks Accelerated using a Shared Graphics Processing Unit |
T. Li, V. K. Narayana and T. El-Ghazawi |
PDF |
| 2011 |
Formulation-level Design Space Exploration for Partially Reconfigurable FPGAs |
R. Kumar and A. Gordon-Ross |
PDF |
| 2011 |
Reflex Barrier: A Scalable Network-Based Synchronization Barrier |
A. Anbar, O. Serres and T. El-Ghazawi |
PDF |
| 2011 |
Spectral Method Characterization of FPGA and GPU Accelerators |
K. Pereira, P. Athanas, H. Lin, and W. Feng |
PDF |
| 2011 |
StreamMR: An Optimized MapReduce Framework for AMD GPUs |
M. Elteir, H.Lin, W. Feng, T. Scogland |
PDF |
| 2011 |
An Architecture for Reconfigurable Multi-core Explorations |
O. Serres, V.K. Narayana and T. El-Ghazawi |
PDF |
| 2011 |
Novo-G: At the Forefront of Scalable Reconfigurable Computing |
A. George, H. Lam, and G. Stitt |
PDF |
| 2011 |
Performance Characterization and Optimization of Atomic Operations on AMD GPUs |
M. Elteir, H. Lin, and W. Feng |
PDF |
| 2011 |
Dual Channel Architecture for Reliable FPGA high Speed Serial Links |
K. Ellsworth, T. Haroldsen, B. Nelson, and M. Wirthlin |
PDF |
| 2011 |
An Integrated Development Toolset and Implementation Methodology for Partially Reconfigurable System-on-Chips |
A. Jara-Berrocal and A. Gordon-Ross |
PDF |
| 2011 |
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs |
C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson and B. Hutchings |
PDF |
| 2011 |
XDL-Based Module Generators for Rapid FPGA Design Implementation |
S. Ghosh and B. Nelson |
PDF |
| 2011 |
Architecture-Aware Mapping and Optimization on a 1600-Core GPU |
M. Daga, T. Scogland, W. Feng |
PDF |
| 2010 |
Voter Insertion Algorithms for FPGA Designs Using Triple Modular Redundancy |
J. Johnson and M. Wirthlin |
PDF |
| 2010 |
Comparative Analysis of HPC and Accelerator Devices: Computation, Memory, I/O, and Power |
J. Richardson, S. Fingulin, D. Raghunathan, C. Massie, A. George, and H. Lam |
PDF |
| 2010 |
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing |
J. Curreri, S. Koehler, A. George, B. Holland, and R. Garcia |
PDF |
| 2010 |
Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing |
M. Huang, V. K. Narayana, H. Simmler, O. Serres, and T. El-Ghazawi |
PDF |
| 2010 |
Accelerating Electrostatic Surface Potential Calculation with Multiscale Approximation on Graphics Processing Units |
R. Anandakrishnan, T. Scogland, A. Fenley, J. Gordon, W. Feng, and A. Onufriev |
PDF |
| 2010 |
High-Level Synthesis Techniques for In-Circuit Assertion-Based Verification |
J. Curreri, G. Stitt, and A. George |
PDF |
| 2010 |
Synchronization Techniques for Crossing Multiple Clock Domains in FPGA-Based TMR Circuits |
Y. Li, B. Nelson, M. Wirthlin |
PDF |
| 2010 |
Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration |
J. Williams, A. George, J. Richardson, K. Gosrani, C. Massie, and H. Lam |
PDF |
| 2010 |
A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems |
C. Reardon, E. Grobelny, A. George, and G. Wang |
PDF |
| 2010 |
Reliable Communications Using FPGAs in High-Radiation Environments - Part 1: Characterization |
B. Pratt, M. Fuller, M. Rice, M. Wirthlin |
PDF |
| 2010 |
Virtual Architectures for Circuit Portability and Fast Placement and Routing |
J. Coole and G. Stitt |
PDF |
| 2010 |
Synchronization Voter Insertion Algorithms for FPGA Designs Using Triple Modular Redundancy |
J. M. Johnson |
PDF |
| 2010 |
On The Use of Rapid Prototyping for Designing PCM/FM Demodulators in FPGAs |
M. Rice, B. Nelson, M. Padilla, and J. Havican |
PDF |
| 2010 |
Performance Modeling for Multilevel Communication in SHMEM+ |
V. Aggarwal, C. Yoon, A. George, H. Lam, and G. Stitt |
PDF |
| 2010 |
A First Look at Integrated GPUs for Green High-Performance Computing, |
T. Scogland, H. Lin, and W. Feng |
PDF |
| 2010 |
Increasing Design Productivity Through Core Reuse, Meta-Data Encapsulation, and Synthesis |
A. Arnesen, K. Ellsworth, D. Gibelyou, T. Haroldsen, J. Havican, M. Padilla, B. Nelson, M. Rice, and M. Wirthlin |
PDF |
| 2010 |
Using Hard Macros to Reduce FPGA Compilation Time |
C. Lavin, M. Padilla, S. Ghosh, B. Nelson, B. Hutchings, and M. Wirthlin |
PDF |
| 2010 |
Reconfigurable Supercomputing with Scalable Systolic Arrays and In-Stream Control for Wavefront Genomics Processing |
C. Pascoe, A. Lawande, H. Lam, A. George, Y. Sun, W. Farmerie, and M. Herbordt |
PDF |
| 2010 |
An Automated Scheduling and Partitioning Algorithm for Scalable RC Systems, |
C. Reardon, A. George, G. Stitt, and H. Lam |
PDF |
